1. Field of Invention
The present invention relates generally to design verification systems for integrated circuits (ICs) and more particularly to the use of hardware-based functional verification systems such as hardware logic emulation or simulation acceleration systems for detecting and analyzing peak power windows.
2. Description of Related Art
Design engineers typically rely on EDA (Electronic Design Automation) tools to develop complex integrated circuits. These EDA tools include a number of hardware-based functional verification systems including logic emulation systems and simulation accelerators. For simplicity these tools will be referred to collectively as emulation systems in the subsequent discussion.
Emulation systems can be used to verify the functionalities of electronic logic designs prior to fabrication of chips or electronic systems. Typical emulation systems utilize either interconnected FPGA (Field Programmable Logic Array) chips or interconnected processor chips. Exemplary hardware logic emulation systems with FPGA devices are described, for example, in U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191, and exemplary hardware logic emulation systems with processor chips are described, for example, in U.S. Pat. Nos. 5,551,013, 6,035,117 and 6,051,030. Each of these patents is incorporated herein by reference in its entirety.
In general, a DUT (Device Under Test) may include an IC or a more complex electronic system. In the case where the DUT corresponds to an IC, it is usually represented in the form of either an RTL (Register Transfer Level) description or a gate level netlist. The gate level netlist may have been derived from RTL sources, including from a hardware description language (HDL), such as Verilog or VHDL (VHSIC (Very High Speed Integrated Circuit) HDL), using a synthesis method. Both RTL and gate level netlists are descriptions of the circuit's components and electrical interconnections between the components, where these components include all logic circuit elements, such as combinatory logic (e.g., gates) and sequential logic (e.g., flip-flops and latches), necessary for implementing a logic circuit.
Emulation systems have certain advantages over software simulation tools, which are typically used to verify block-level models of a user's design. Software simulators run on a computer system or workstation, typically in serial operations with a single or a small number of CPUs (Central Processing Units). In contrast, emulation systems have dedicated hardware that will perform the designed functions in parallel. This massive parallelism enables an emulation system to operate at a speed that is orders of magnitude faster than a software simulator. Because emulators can operate so much faster than simulators, they can perform functional verification much faster. For example, an emulator can execute thousands of clock cycles of a DUT in a few milliseconds. Thus, in the same amount of time an emulator executes millions of clock cycles, a software simulator might only have simulated the execution of a few or even just a fraction of a clock cycle. In fact, emulators can operate at speed fast enough to allow the intended application software to run on the prototype system, which is something the software simulator can never accomplish.
Another advantage of emulation systems over software simulators is their ability to operate “in circuit.” Operating “in circuit” refers to an emulator's ability to operate in the actual hardware that the DUT being emulated will eventually be installed into once the chip has been fabricated. This actual hardware is sometimes referred to as the “target system.” For example, the designer of a microprocessor might emulate the microprocessor design. Using cables connecting the emulator to the motherboard of a personal computer, the emulator can be used in lieu of the actual microprocessor. The ability to operate in circuit provides many advantages. One of them is that the designer can see how their design functions in the actual system in which the DUT will eventually be installed. Another advantage is that in circuit emulation allows software development to take place before the IC chip is fabricated. Thus, the emulator can emulate the IC in the target system while the design team writes and tests firmware or other application software.
Integrated circuits designed for low-power applications (e.g., for wireless and portable electronics) have additional challenges for design verification including minimizing power dissipation, designing efficient packaging and cooling systems for high-power integrated circuits, and verifying functionalities of low-power or no power situations early in the design. These power management issues have become even more critical in view of the continuous shrinking of device dimensions with the advancement of semiconductor processing technology.
However, conventional emulation systems have not responded to these challenges. One reason is that existing power optimization and implementation techniques are typically applied at the physical implementation phase of the design process (e.g., after circuit synthesis). These power management design techniques may significantly change the design constraints, yet none of the intended behavior can be captured in the RTL of the design. This deficiency creates a gap in the RTL to Graphic Data System II (GDSII) implementation and verification flow where the original RTL can no longer be relied upon as a complete representation of the design, and thus cannot be used to verify the final netlist implementation containing power management implementations.
With higher levels of integration, power estimation has become an increasingly critical issue for chip design, especially for low-power designs. See, for example, patent application US 2006/0277509 A1, published Dec. 7, 2006, which is incorporated herein by reference in its entirety. Identifying all high power consumption scenarios is a challenging task in power analysis. However, conventional power analysis tools, which usually base their power calculations on design activity files with common formats such as TCF (Toggle Count Format) or SAIF (Switching Activity Interchange Format), typically report only the average power consumption for a given time period. Additionally, power analysis tools based on VCD (Value Change Dump) for calculating peak power values are usually time-consuming and often not practical for large complex designs, particularly when applied to relatively long test sequences that replicate conditions for the final silicon. Thus, conventional approaches have not adequately enabled hardware-based verification of critical power management functions such as power estimation and peak power detection.
Thus there is a need for improved emulation systems for detecting and analyzing peak power windows of IC designs.